1. Field of the Invention
The present invention generally relates to fabricating an n-channel FET and p-channel FET on the same wafer in a manner that optimizes carrier transport for each device. Specifically, on a Germanium layer an n-channel FET is fabricated on the (111) surface in the <110> direction and a p-channel FET is fabricated on the (100) surface in the <110> direction.
2. Description of the Related Art
Carrier transport in the germanium field effect transistor (Ge FET) is known to be enhanced relative to silicon field effect transistors. The prior art, therefore, recognizes that germanium provides a superior electron mobility compared to silicon. Additionally, the prior art commonly combines nFETs and pFETs on a single wafer for CMOS circuits. What is missing in the prior art, however, is an optimization of the structure and orientation of the complementary devices, as based on characteristics of carrier mobility.